View ICS843204I_329772.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Four 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 155.52MHz and 156.25MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 13MHz): 0.86ps (typical) * RMS phase jitter @ 156.25MHz, using a 19.44MHz crystal (1.875MHz - 20MHz): 0.52ps (typical) * Full 3.3V supply mode * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS843204I is a 4 output LVPECL Synthesizer optimized to generate Gigabit HiPerClockSTM Ethernet and SONET reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal, 155.52MHz and 156.25MHz frequencies can be generated. The ICS843204I uses ICS' FemtoClock TM low phase noise VCO technology and can achieve 1ps or lower typical RMS phase jitter. The ICS843204I is packaged in a 48-pin TSSOP package.
IC S
BLOCK DIAGRAM
PLL_BYPASS_A IN_SELA CLK0 XTAL_IN0 25MHz SELA0 OEA0
PIN ASSIGNMENT
nQA1 QA1 nQA0 QA0 nc VCCO_A SELA1 SELA0 PLL_BYPASS_A nc nc nc nc XTAL_IN1 XTAL_OUT1 CLK1 IN_SEL_B PLL_BYPASS_B VCCO_B nc QB0 nQB0 QB1 nQB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 IN_SEL_A CLK0 XTAL_IN0 XTAL_OUT0 nc VEE OEA0 OEA1 VCC VCCA nc nc SELB0 VEE OEB0 OEB1 VCC SELB1 VCCA nc nc nc nc nc
OSC
XTAL_OUT0
PLL
/4
156.25MHz
0 1
SELA1 OEA1
QA0 nQA0
625MHz
0 1
PLL_BYPASS_B IN_SELB CLK1
19.44MHz
QA1 nQA1
SELB0 OEB0
XTAL_IN1
0
QB0 nQB0
OSC
XTAL_OUT1
PLL
622.08MHz
/4
155.52MHz
1
SELB1 OEB1
ICS843204I
QB1 nQB1
0 1
48 Lead TSSOP 6.1mm x 12.5mm x 0.93mm package body G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843204AGI www.icst.com/products/hiperclocks.html REV. A JANUARY 6, 2006
1
PRELIMINARY
Integrated Circuit Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 10, 11, 12, 13, 20, 25, 26, 27, 28, 29, 37, 38, 44 6 7 Name nQA1, QA1 nQA0, QA0 nc VCCO_A SELA1 Type Output Output Unused Power Input Description
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. No connect. Output supply pin for Bank A outputs. Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. Pulldown When LOW, selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. Pulldown When LOW, selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active. Parallel resonant crystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Pulldown LVCMOS/LVTTL clock inputs. Differential output pair. LVPECL interface levels. Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects CLK1 input. LVCMOS/LVTTL interface levels. When LOW, PLL is bypassed. When HIGH, PLL output is active. Output supply pin for Bank B outputs. Differential output pair. LVPECL interface levels. Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW, selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels. Analog supply pins.
8 9 14, 15 16, 47 21, 22 17 18 19 23, 24 31 30, 39 32, 40
SELA0 PLL_BYPASS_A XTAL_IN1, XTAL_OUT1 CLK1, CLK0 QB0, nQB0 IN_SEL_B PLL_BYPASS_B VCCO_B QB1, nQB1 SELB1 VCCA VCC
Input Input Input Input Ouput Input Input Power Ouput Input Power Power
Pullup Pullup
Pullup
Core supply pins. Output enable pin. QB1/nQB1 outputs are enable. 33 OEB1 Input Pullup LVCMOS/LVTTL interface levels. Output enable pin. QB0/nQB0 outputs are enabled. 34 OEB0 Input Pullup LVCMOS/LVTTL interface levels. Power Negative supply pins. 35, 43 VEE Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW, selects QB0/nQB0 at 156.25MHz. 36 SELB0 Input Pullup LVCMOS/LVTTL interface levels. Output enable pin. QA1/nQA1 outpus are enabled. 41 OEA1 Input Pullup LVCMOS/LVTTL interface levels. Output enable pin. QA0/nQA0 outputs are enabled. 42 OEA0 Input Pullup LVCMOS/LVTTL interface levels. XTAL_OUT0, Parallel resonant crystal interface. XTAL_OUT0 is the output, 45, 46 Input XTAL_IN0 is the input. XTAL_IN0 Select pin. When HIGH, selects XTAL0 inputs. When LOW, 48 IN_SEL_A Input Pullup selects CLK0 input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP
843204AGI
Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF k k
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current
Package Thermal Impedance, JA 58.3C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V10%, TA = -40C TO 85C
Symbol VCC VCCA VCCO_A, VCCO_B IEE ICC ICCA ICCO_A, ICCO_B Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.97 2.97 2.97 Typical 3.3 3.3 3.3 125 92 14 16 Maximum 3.63 3.63 3.63 Units V V V mA mA mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V10%, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK0, CLK1, SELA0, SELA1 IIH Input High Current PLL_BYPASS_A, PLL_BYPASS_B, IN_SEL_A, IN_SEL_B, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 CLK0, CLK1, SELA0, SELA1 IIL Input Low Current PLL_BYPASS_A, PLL_BYPASS_B, IN_SEL_A, IN_SEL_B, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 Test Conditions Minimum Typical 2 -0.3 VCC = VIN = 3.63V Maximum VCC + 0.3 0.8 150 Units V V A
VCC = VIN = 3.63V
5
A
VCC = 3.63V, VIN = 0V
-5
A
VCC = 3.63V, VIN = 0V
-150
A
843204AGI
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V10%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. 19.44 Test Conditions Minimum Typical Maximum 25 50 7 1 Units MHz pF mW Fundamental
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V10%, TA = -40C TO 85C
Symbol fOUT t sk(o) t jit(O) t R / tF Parameter Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time 155.52MHz, (12kHz - 1.3MHz) 156.25MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions SELB0 = 1; OEB0 = 1 SELA0 = 0; OEA0 = 1 Minimum Typical 155.52 156.25 TBD 0.86 0.52 475 Maximum Units MHz MHz ps ps ps ps %
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: See Phase Noise plot.
843204AGI
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC , VCCA, VCCO_X
Qx
SCOPE
nQx Qx nQy
LVPECL
nQx
Qy
tsk(o)
VEE
-1.3V 0.33V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQA0, nQA1 nQB0, nQB1 QA0, QA1 QB0, QB1
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843204AGI
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843204I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843204I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
ICS843204I
Figure 2. CRYSTAL INPUt INTERFACE
843204AGI
www.icst.com/products/hiperclocks.html
6
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843204AGI
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843002 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 125mA = 453.75mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.63V, with all outputs switching) = 453.75mW + 120mW = 573.75mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 52.3C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.574W * 52.3C/W = 115C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 48-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0 82.6C/W 58.3C/W 200 70.3C/W 52.3C/W 500 63.7C/W 49.9C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843204AGI
www.icst.com/products/hiperclocks.html
8
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843204AGI
www.icst.com/products/hiperclocks.html
9
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 48 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 82.6C/W 58.3C/W 200 70.3C/W 52.3C/W 500 63.7C/W 49.9C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843204I is: 4090
843204AGI
www.icst.com/products/hiperclocks.html
10
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 48 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -6.00 0.50 BASIC 0.75 8 0.10 -0.05 0.80 0.17 0.09 12.40 8.10 BASIC 6.20 Millimeters Minimum 48 1.20 0.15 1.05 0.27 0.20 12.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
843204AGI
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843204I
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Marking Package 48 Lead TSSOP 48 Lead TSSOP 48 Lead "Lead-Free" TSSOP 48 Lead "Lead-Free" TSSOP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843204AGI ICS843204AGIT ICS843204AGILF ICS843204AGILFT ICS843204AGI ICS843204AGI TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843204AGI
www.icst.com/products/hiperclocks.html
12
REV. A JANUARY 6, 2006

▲Up To Search▲

Price & Availability of ICS843204I

	To Download ICS843204I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .